The present invention relates generally to flip-flop circuits, and more particularly, to a system for providing a symmetric pulse generator flip-flop.
There is an ongoing demand for electronic devices that provide more and faster functionality, while requiring less power. As a result, electronic devices, such as personal computers, are designed to use faster and faster clock frequencies. However, with the increase in clock frequencies, clock-related power consumption is taking an increasing portion of the available power. For example, high-speed memories generally require more power than lower speed memories.
In a move to reduce clock-related power consumption, dual edge-triggered storage elements (DETSE) have been used. A DETSE samples data at each transition of an input clock signal as opposed to conventionally used clocked storage elements referred to as single edge-triggered storage elements (SETSE), which capture data at their input based on one clock transition only.
Dual-edge clocking can potentially achieve roughly the same throughput with half of the clock frequency and thus consume only half of the clock-related power, as opposed to a SETSE designed circuit. However, in order to keep timing overhead low, dual-edge clocking requires tight control of the clock duty cycle and uncertainties related to both clock edges. Thus, because of the large circuit complexity, due to the need to capture data at two clock edges rather than one, current DETSE circuits may exhibit larger delays and power consumption than their single edge-triggered counterparts.
Therefore, it would be desirable to have a DETSE that is designed to have low power and fast operating speeds.
The present invention includes a Symmetric Pulse Generator Flip-Flop (SPG-FF). In one embodiment, a flip-flop constructed in accordance with the present invention comprises two pulse generator stages that each respond to one particular transition of an input clock signal. Thus, the flip-flop is triggered on both the rising and falling edge of the clock signal to capture an input data signal. The outputs of the generator stages are combined to form a flip-flop output. As a result, a flip-flop constructed in accordance with the present invention provides comparatively faster operating speed and lower power than conventional circuits.
In one embodiment included in the present invention, a symmetric pulse generator (SPG) flip-flop is provided that operates to receive an input data signal and an input clock signal to produce a flip-flop output signal. The SPG flip-flop comprises clock logic that receives the input clock signal and produces first, second, and third timing signals. The generator also comprises a first pulse generator stage that receives the input data signal, the input clock signal, and the first timing signal, and generates a first generator output signal. The SPG flip-flop also comprises a second pulse generator stage that receives the input data signal, and the second and third timing signals, and generates a second generator output signal. The SPG flip-flop also comprises logic to combine the first and second generator output signals to produce the flip-flop output signal.
In another embodiment included in the present invention, a method for providing an SPG flip-flop that operates to receive an input data signal and an input clock signal to produce a flip-flop output signal is provided. The method comprises steps of producing first, second, and third timing signals from the input clock signal, generating a first generator output signal from the input data signal, the input clock signal, and the first timing signal, generating a second generator output signal from the input data signal, and the second and third timing signals, and combining the first and second generator output signals to produce the flip-flop output signal.